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Then install latest version of php

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Error 2:

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Linux compilers

C/C++ Compiler for linux os through bash script

Hello friends i had developed c and c++ compilr through bash scripting

Download C compilr here


Download C++ compilr here

How to run the file

First download the file to desktop

open the linux terminal and change directory to desktop

to run the bash script you type sh scirptfilename.sh as shown in the figure
for c compilr

for c++ compilr


and press enter to run it starts working


Contact me:

VDHL programming

VHDL Structural Modeling of Full adder with xor,or,and gate

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Full_Adder is

    Port ( a,b,cin : in  STD_LOGIC;

           s,cout : out  STD_LOGIC);

end Full_Adder;

architecture Behavioral of Full_Adder is

component xor_g is

    Port ( x,y : in  STD_LOGIC;

           z : out  STD_LOGIC);

end component;

component or_g is

    Port ( x,y : in  STD_LOGIC;

           z : out  STD_LOGIC);

end component;

component and_g is

    Port ( x,y : in  STD_LOGIC;

           z : out  STD_LOGIC);

end component;

signal s1,s2,s3: std_logic;

begin

U1: xor_g port map(a,b,s1);

U2: and_g port map(a,b,s3);

U3: xor_g port map(s1,cin,s);

U4: and_g port map(s1,cin,s2);

U5: or_g port map(s2,s3,cout);

end Behavioral;

Test bench 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY FA_test IS
END FA_test;

ARCHITECTURE behavior OF FA_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Full_Adder
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         cin : IN  std_logic;
         s : OUT  std_logic;
         cout : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal cin : std_logic := '0';

     --Outputs
   signal s : std_logic;
   signal cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant  period : time := 100 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Full_Adder PORT MAP (
          a => a,
          b => b,
          cin => cin,
          s => s,
          cout => cout
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin      
      -- hold reset state for 100 ns.
     wait for 50 ns;  
     a <= '0';
      b <= '0';
      cin <= '0';
      wait for 50 ns;  
     a <= '0';
      b <= '0';
      cin <= '1';
     wait for 50 ns;  
     a <= '0';
      b <= '1';
      cin <= '0';    
      wait for 50 ns;  
     a <= '0';
      b <= '1';
      cin <= '1';
     wait for 50 ns;  
     a <= '1';
      b <= '0';
      cin <= '0';
     wait for 50 ns;  
     a <= '1';
      b <= '0';
      cin <= '1';
      wait for 50 ns;  
     a <= '1';
      b <= '1';
      cin <= '0';
     wait for 50 ns;  
     a <= '1';
      b <= '1';
      cin <= '1';


      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;
 

 

VHDL programming

VHDL Structural Model design of Full Adder using two Half Adders

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FA is
    Port ( a,b,cin : in  STD_LOGIC;
           sum,cout : out  STD_LOGIC);
end FA;

architecture Behavioral of FA is

component HA is
Port (a,b: in std_logic;
      sum,carry : out std_logic);
end component;

component or_g is
Port ( x,y : in  STD_LOGIC;
           f : out  STD_LOGIC);
end component;

signal s1,s2,s3 : std_logic ;
begin
U1: HA port map(a,b,s1,s2);
U2: HA port map(s1,cin,sum,s3);
U3: or_g port map(s3,s2,cout);
end Behavioral;

Test bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY HA_HALFADDER_test IS
END HA_HALFADDER_test;

ARCHITECTURE behavior OF HA_HALFADDER_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT FA
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         cin : IN  std_logic;
         sum : OUT  std_logic;
         cout : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal cin : std_logic := '0';

     --Outputs
   signal sum : std_logic;
   signal cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: FA PORT MAP (
          a => a,
          b => b,
          cin => cin,
          sum => sum,
          cout => cout
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;   
        a <= '0';
        b <= '0';
        cin <= '0';
      wait for 100 ns;   
        a <= '0';
        b <= '0';
        cin <= '1';
      wait for 100 ns;   
        a <= '0';
        b <= '1';
        cin <= '0';
      wait for 100 ns;   
        a <= '0';
        b <= '1';
        cin <= '1';
      wait for 100 ns;   
        a <= '1';
        b <= '0';
        cin <= '0';
      wait for 100 ns;   
        a <= '1';
        b <= '0';
        cin <= '1';
      wait for 100 ns;   
        a <= '1';
        b <= '1';
        cin <= '0';
      wait for 100 ns;   
        a <= '1';
        b <= '1';
        cin <= '1';       
      wait for  period*10;

      -- insert stimulus here

      wait;
   end process;

END;

Simulation result

Circuit Design with VHDL A book by Volnei A. Pedroni

Circuit Design with VHDL A book by Volnei A. Pedroni

Published on 2004

Read Now

VHDL Programming

Design of Full Adder using 8:1 Multiplexer using vhdl code 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity famux is
    Port ( sel : in  STD_LOGIC_VECTOR(2 downto 0);
           sum,carry : out  STD_LOGIC);
end famux;

architecture Behavioral of famux is

begin
with sel select sum <=
'0'  when "000",
'0'  when "011",
'0'  when "101",
'0'  when "110",
'1'  when "001",
'1'  when "010",
'1'  when "100",
'1'  when "111",
'0' when others;

with sel select carry <=
'0'  when "000",
'1'  when "011",
'1'  when "101",
'1'  when "110",
'0'  when "001",
'0'  when "010",
'0'  when "100",
'1'  when "111",
'0' when others;

end Behavioral;

Verilog programming

VERILOG BASIC LOGIC GATES

AND GATE

`timescale 1ns / 1ps
 module and_gate(
    input a,b,
    output c
    );

assign c = a & b;
endmodule

TEST FIXTURE

`timescale 1ns / 1ps
 
module tf_testbenchlog;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    and_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

OR GATE

`timescale 1ns / 1ps
 module or_gate(
    input a,b,
    output c
    );

or (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps

 module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    or_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

NOT GATE

`timescale 1ns / 1ps
 module not_gate(
    input a,
    output y
    );

not (y,a);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps

 module tf_testfixture;

    // Inputs
    reg a;

    // Outputs
    wire y;

    // Instantiate the Unit Under Test (UUT)
    not_gate uut (
        .a(a),
        .y(y)
    );

    initial begin
        // Initialize Inputs
        a = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
       
        #100;
        a = 1'b1;
       
        #100;
        a = 1'b0;
       
        #100;
        a = 1'b1;
       
       
        // Add stimulus here

    end
     
endmodule

NAND GATE

`timescale 1ns / 1ps
 module nand_gate(
    input a,b,
    output c
    );

nand (c,a,b);
endmodule

TEST FIXTURES

`timescale 1ns / 1ps

 
module tf_testfixtures;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    nand_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

NOR GATE

`timescale 1ns / 1ps
 module nor_gate(
    input a,b,
    output c
    );

nor (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps

module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    nor_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

 XOR GATE

`timescale 1ns / 1ps
 module xor_gate(
    input a,b,
    output c
    );

xor (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps


module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    xor_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

XNOR GATE

`timescale 1ns / 1ps
 module xnor_gate(
    input a,b,
    output c
    );

xnor (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps


module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    xnor_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule