VHDL programming

VHDL Structural Model design of Full Adder using two Half Adders

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FA is
    Port ( a,b,cin : in  STD_LOGIC;
           sum,cout : out  STD_LOGIC);
end FA;

architecture Behavioral of FA is

component HA is
Port (a,b: in std_logic;
      sum,carry : out std_logic);
end component;

component or_g is
Port ( x,y : in  STD_LOGIC;
           f : out  STD_LOGIC);
end component;

signal s1,s2,s3 : std_logic ;
begin
U1: HA port map(a,b,s1,s2);
U2: HA port map(s1,cin,sum,s3);
U3: or_g port map(s3,s2,cout);
end Behavioral;

Test bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY HA_HALFADDER_test IS
END HA_HALFADDER_test;

ARCHITECTURE behavior OF HA_HALFADDER_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT FA
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         cin : IN  std_logic;
         sum : OUT  std_logic;
         cout : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal cin : std_logic := '0';

     --Outputs
   signal sum : std_logic;
   signal cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: FA PORT MAP (
          a => a,
          b => b,
          cin => cin,
          sum => sum,
          cout => cout
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;   
        a <= '0';
        b <= '0';
        cin <= '0';
      wait for 100 ns;   
        a <= '0';
        b <= '0';
        cin <= '1';
      wait for 100 ns;   
        a <= '0';
        b <= '1';
        cin <= '0';
      wait for 100 ns;   
        a <= '0';
        b <= '1';
        cin <= '1';
      wait for 100 ns;   
        a <= '1';
        b <= '0';
        cin <= '0';
      wait for 100 ns;   
        a <= '1';
        b <= '0';
        cin <= '1';
      wait for 100 ns;   
        a <= '1';
        b <= '1';
        cin <= '0';
      wait for 100 ns;   
        a <= '1';
        b <= '1';
        cin <= '1';       
      wait for  period*10;

      -- insert stimulus here

      wait;
   end process;

END;

Simulation result