VHDL Programming

Design of Full Adder using 8:1 Multiplexer using vhdl code 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity famux is
    Port ( sel : in  STD_LOGIC_VECTOR(2 downto 0);
           sum,carry : out  STD_LOGIC);
end famux;

architecture Behavioral of famux is

begin
with sel select sum <=
'0'  when "000",
'0'  when "011",
'0'  when "101",
'0'  when "110",
'1'  when "001",
'1'  when "010",
'1'  when "100",
'1'  when "111",
'0' when others;

with sel select carry <=
'0'  when "000",
'1'  when "011",
'1'  when "101",
'1'  when "110",
'0'  when "001",
'0'  when "010",
'0'  when "100",
'1'  when "111",
'0' when others;

end Behavioral;