VDHL programming

VHDL Structural Modeling of Full adder with xor,or,and gate

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Full_Adder is

    Port ( a,b,cin : in  STD_LOGIC;

           s,cout : out  STD_LOGIC);

end Full_Adder;

architecture Behavioral of Full_Adder is

component xor_g is

    Port ( x,y : in  STD_LOGIC;

           z : out  STD_LOGIC);

end component;

component or_g is

    Port ( x,y : in  STD_LOGIC;

           z : out  STD_LOGIC);

end component;

component and_g is

    Port ( x,y : in  STD_LOGIC;

           z : out  STD_LOGIC);

end component;

signal s1,s2,s3: std_logic;

begin

U1: xor_g port map(a,b,s1);

U2: and_g port map(a,b,s3);

U3: xor_g port map(s1,cin,s);

U4: and_g port map(s1,cin,s2);

U5: or_g port map(s2,s3,cout);

end Behavioral;

Test bench 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY FA_test IS
END FA_test;

ARCHITECTURE behavior OF FA_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Full_Adder
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         cin : IN  std_logic;
         s : OUT  std_logic;
         cout : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal cin : std_logic := '0';

     --Outputs
   signal s : std_logic;
   signal cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant  period : time := 100 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Full_Adder PORT MAP (
          a => a,
          b => b,
          cin => cin,
          s => s,
          cout => cout
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin      
      -- hold reset state for 100 ns.
     wait for 50 ns;  
     a <= '0';
      b <= '0';
      cin <= '0';
      wait for 50 ns;  
     a <= '0';
      b <= '0';
      cin <= '1';
     wait for 50 ns;  
     a <= '0';
      b <= '1';
      cin <= '0';    
      wait for 50 ns;  
     a <= '0';
      b <= '1';
      cin <= '1';
     wait for 50 ns;  
     a <= '1';
      b <= '0';
      cin <= '0';
     wait for 50 ns;  
     a <= '1';
      b <= '0';
      cin <= '1';
      wait for 50 ns;  
     a <= '1';
      b <= '1';
      cin <= '0';
     wait for 50 ns;  
     a <= '1';
      b <= '1';
      cin <= '1';


      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;