VHDL BASIC GATES WITH TEST BENCH
AND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;
architecture Behavioral of and_gate is
begin
c <= a and b;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbenchprogram IS
END testbenchprogram;
ARCHITECTURE behavior OF testbenchprogram IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT and_gate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: and_gate PORT MAP (
a => a,
b => b,
c => c
);
-- Clock process definitions
-- process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= '0';
wait for 100ns;
b <= '1';
wait for 100ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for period*10;
-- insert stimulus here
wait;
end process;
END;
OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;
architecture Behavioral of or_gate is
begin
c <= a or b ;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbenchessprograms IS
END testbenchessprograms;
ARCHITECTURE behavior OF testbenchessprograms IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT or_gate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: or_gate PORT MAP (
a => a,
b => b,
c => c
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= '0';
wait for 100ns;
b <= '1';
wait for 100ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for period*10;
-- insert stimulus here
wait;
end process;
END;
NOT GATE
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entity not_gate is
Port ( a : in STD_LOGIC;
y : out STD_LOGIC);
end not_gate;
architecture Behavioral of not_gate is
begin
y <= not a;
end Behavioral;
TEST BENCH
LIBRARY ieee;USE ieee.std_logic_1164.ALL;
ENTITY testbecnhes IS
END testbecnhes;
ARCHITECTURE behavior OF testbecnhes IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT not_gate
PORT(
a : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
--Outputs
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: not_gate PORT MAP (
a => a,
y => y
);
--
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 200 ns;
a <= '0';
wait for 100 ns;
a <= '1';
wait for 100 ns;
a <= '1';
wait for period*10;
-- insert stimulus here
wait;
end process;
END;
NAND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end nand_gate;
architecture Behavioral of nand_gate is
begin
c <= a nand b;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbechces IS
END testbechces;
ARCHITECTURE behavior OF testbechces IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nand_gate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: nand_gate PORT MAP (
a => a,
b => b,
c => c
);
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= '0';
wait for 100ns;
b <= '1';
wait for 100ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for period*10;
-- insert stimulus here
wait;
end process;
END;
NOR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nor_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end nor_gate;
architecture Behavioral of nor_gate is
begin
c <= a nor b ;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbecnhes IS
END testbecnhes;
ARCHITECTURE behavior OF testbecnhes IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nor_gate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: nor_gate PORT MAP (
a => a,
b => b,
c => c
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= '0';
wait for 100ns;
b <= '1';
wait for 100ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for period*10;
-- insert stimulus here
wait;
end process;
END;
XOR GATE
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity xor_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_gate;
architecture Behavioral of xor_gate is
begin
c <= a xor b;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbeches IS
END testbeches;
ARCHITECTURE behavior OF testbeches IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xor_gate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xor_gate PORT MAP (
a => a,
b => b,
c => c
);
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= '0';
wait for 100ns;
b <= '1';
wait for 100ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for period*10;
-- insert stimulus here
wait;
end process;
END;
XNOR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xnor_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end xnor_gate;
architecture Behavioral of xnor_gate is
begin
c <= a xnor b ;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbenchs IS
END testbenchs;
ARCHITECTURE behavior OF testbenchs IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xnor_gate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xnor_gate PORT MAP (
a => a,
b => b,
c => c
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= '0';
wait for 100ns;
b <= '1';
wait for 100ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for period*10;
-- insert stimulus here
wait;
end process;
END;
