Circuit Design with VHDL A book by Volnei A. Pedroni

Circuit Design with VHDL A book by Volnei A. Pedroni

Published on 2004

Read Now

VHDL Programming

Design of Full Adder using 8:1 Multiplexer using vhdl code 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity famux is
    Port ( sel : in  STD_LOGIC_VECTOR(2 downto 0);
           sum,carry : out  STD_LOGIC);
end famux;

architecture Behavioral of famux is

begin
with sel select sum <=
'0'  when "000",
'0'  when "011",
'0'  when "101",
'0'  when "110",
'1'  when "001",
'1'  when "010",
'1'  when "100",
'1'  when "111",
'0' when others;

with sel select carry <=
'0'  when "000",
'1'  when "011",
'1'  when "101",
'1'  when "110",
'0'  when "001",
'0'  when "010",
'0'  when "100",
'1'  when "111",
'0' when others;

end Behavioral;

Verilog programming

VERILOG BASIC LOGIC GATES

AND GATE

`timescale 1ns / 1ps
 module and_gate(
    input a,b,
    output c
    );

assign c = a & b;
endmodule

TEST FIXTURE

`timescale 1ns / 1ps
 
module tf_testbenchlog;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    and_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

OR GATE

`timescale 1ns / 1ps
 module or_gate(
    input a,b,
    output c
    );

or (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps

 module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    or_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

NOT GATE

`timescale 1ns / 1ps
 module not_gate(
    input a,
    output y
    );

not (y,a);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps

 module tf_testfixture;

    // Inputs
    reg a;

    // Outputs
    wire y;

    // Instantiate the Unit Under Test (UUT)
    not_gate uut (
        .a(a),
        .y(y)
    );

    initial begin
        // Initialize Inputs
        a = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
       
        #100;
        a = 1'b1;
       
        #100;
        a = 1'b0;
       
        #100;
        a = 1'b1;
       
       
        // Add stimulus here

    end
     
endmodule

NAND GATE

`timescale 1ns / 1ps
 module nand_gate(
    input a,b,
    output c
    );

nand (c,a,b);
endmodule

TEST FIXTURES

`timescale 1ns / 1ps

 
module tf_testfixtures;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    nand_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

NOR GATE

`timescale 1ns / 1ps
 module nor_gate(
    input a,b,
    output c
    );

nor (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps

module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    nor_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

 XOR GATE

`timescale 1ns / 1ps
 module xor_gate(
    input a,b,
    output c
    );

xor (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps


module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    xor_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

XNOR GATE

`timescale 1ns / 1ps
 module xnor_gate(
    input a,b,
    output c
    );

xnor (c,a,b);
endmodule

TEST FIXTURE

`timescale 1ns / 1ps


module tf_testfixture;

    // Inputs
    reg a;
    reg b;

    // Outputs
    wire c;

    // Instantiate the Unit Under Test (UUT)
    xnor_gate uut (
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a = 1'b0;
        b = 1'b0;
        #100;
        a = 1'b0;
        b = 1'b1;
        #100;
        a = 1'b1;
        b = 1'b0;
        #100;
        a = 1'b1;
        b = 1'b1;
       
        // Add stimulus here

    end
     
endmodule

VHDL test bench

VHDL BASIC GATES WITH TEST BENCH

AND GATE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_gate is
    Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end and_gate;

architecture Behavioral of and_gate is

begin
c <= a and b;

end Behavioral;

TEST BENCH

 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY testbenchprogram IS
END testbenchprogram;

ARCHITECTURE behavior OF testbenchprogram IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT and_gate
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

     --Outputs
   signal c : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: and_gate PORT MAP (
          a => a,
          b => b,
          c => c
        );

   -- Clock process definitions
--   process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
     wait for 100 ns;   
        a <= '0';
        wait for 100ns;
        b <= '1';
        wait for 100ns;
        a <= '1';
        b <= '0';
        wait for 100 ns;
        a <= '1';
        b <= '1';

      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;

OR GATE

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 entity or_gate is
    Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end or_gate;

architecture Behavioral of or_gate is

begin
c <= a or b ;
end Behavioral;

TEST BENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY testbenchessprograms IS
END testbenchessprograms;

ARCHITECTURE behavior OF testbenchessprograms IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT or_gate
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

     --Outputs
   signal c : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 100 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: or_gate PORT MAP (
          a => a,
          b => b,
          c => c
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;   
        a <= '0';
        wait for 100ns;
        b <= '1';
        wait for 100ns;
        a <= '1';
        b <= '0';
        wait for 100 ns;
        a <= '1';
        b <= '1';

      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;

NOT GATE

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity not_gate is
    Port ( a : in  STD_LOGIC;
           y : out  STD_LOGIC);
end not_gate;

architecture Behavioral of not_gate is

begin

y <= not a;

end Behavioral;

TEST BENCH

 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 ENTITY testbecnhes IS
END testbecnhes;

ARCHITECTURE behavior OF testbecnhes IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT not_gate
    PORT(
         a : IN  std_logic;
         y : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';

     --Outputs
   signal y : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 100 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: not_gate PORT MAP (
          a => a,
          y => y
        );
--
--   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 200 ns;   
      a <= '0';
        wait for 100 ns;   
      a <= '1';
      wait for 100 ns;   
      a <= '1';
      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;

NAND GATE

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity nand_gate is
    Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end nand_gate;

architecture Behavioral of nand_gate is

begin

c <= a nand b;
end Behavioral;

TEST BENCH

 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY testbechces IS
END testbechces;

ARCHITECTURE behavior OF testbechces IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT nand_gate
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

     --Outputs
   signal c : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 100 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: nand_gate PORT MAP (
          a => a,
          b => b,
          c => c
        );

--   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;   
        a <= '0';
        wait for 100ns;
        b <= '1';
        wait for 100ns;
        a <= '1';
        b <= '0';
        wait for 100 ns;
        a <= '1';
        b <= '1';

      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;

NOR GATE

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity nor_gate is
    Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end nor_gate;

architecture Behavioral of nor_gate is

begin

c <= a nor b ;

end Behavioral;

TEST BENCH

 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY testbecnhes IS
END testbecnhes;

ARCHITECTURE behavior OF testbecnhes IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT nor_gate
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

     --Outputs
   signal c : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: nor_gate PORT MAP (
          a => a,
          b => b,
          c => c
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;
--

   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
  
    wait for 100 ns;   
        a <= '0';
        wait for 100ns;
        b <= '1';
        wait for 100ns;
        a <= '1';
        b <= '0';
        wait for 100 ns;
        a <= '1';
        b <= '1';
      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;

XOR GATE

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xor_gate is
    Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end xor_gate;

architecture Behavioral of xor_gate is

begin

c <= a xor b;

end Behavioral;

TEST BENCH

 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY testbeches IS
END testbeches;

ARCHITECTURE behavior OF testbeches IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT xor_gate
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

     --Outputs
   signal c : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 100 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: xor_gate PORT MAP (
          a => a,
          b => b,
          c => c
        );

--   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;       
        a <= '0';
        wait for 100ns;
        b <= '1';
        wait for 100ns;
        a <= '1';
        b <= '0';
        wait for 100 ns;
        a <= '1';
        b <= '1';

      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;

XNOR GATE

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity xnor_gate is
    Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end xnor_gate;

architecture Behavioral of xnor_gate is

begin

c <= a xnor b ;

end Behavioral;

TEST BENCH

 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY testbenchs IS
END testbenchs;

ARCHITECTURE behavior OF testbenchs IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT xnor_gate
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

     --Outputs
   signal c : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant period : time := 100 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: xnor_gate PORT MAP (
          a => a,
          b => b,
          c => c
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--        <clock> <= '0';
--        wait for <clock>_period/2;
--        <clock> <= '1';
--        wait for <clock>_period/2;
--   end process;


   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;   
        a <= '0';
        wait for 100ns;
        b <= '1';
        wait for 100ns;
        a <= '1';
        b <= '0';
        wait for 100 ns;
        a <= '1';
        b <= '1';

      wait for period*10;

      -- insert stimulus here

      wait;
   end process;

END;

Internet Download Manager

INTERNET DOWNLOAD MANAGER

 

Download Here

 

Instructions to install this software

1.    Download IDM with crack in this blog

2.    Unzip IDM with crack to desktop

3.    Install the latest IDM and open IDM

4.    Here you will find idm Fake Serial Number will notice, but do not worry

Copy the file "IDM Crack" folder to install IDM

With Windows 64bit C: \ Program Files (x86) \ Internet Download Manager
With Windows 32bit C: \ Program Files \ Internet Download Manager

Then run the IDM CRACK : click Patch

5    OK IDM crack finished, Enjoy

Password for the file 

password:DOCUMENT

 

Xlinix support for windows 8.1 x64bit

Xlinix Support Guide for windows 8 and windows 8.1 x64bit architecture 

 

Go to  

C:\Xilinx\14.5\ISE_DS\ISE\lib\nt64

 

find libPortability.dll

rename that file to libPortability.dll.orig

find libPortabilityNOSH.dll

and make copy of libPortabilityNOSH.dll

and rename it to libPortability.dll

Similarly Do this 

or else copy renamed libPortability.dll

to

C:\Xilinx\14.5\ISE_DS\common\lib\nt64

This turns off SmartHeap.

This will fix ISE and iMPACT crashes on file dialogs.

UHARC STANDOLONE

UHARC 6.0b Standolone Version 

Password:  COM